Simplifying System on Chip Design and Manufacture

CMC / SoC Labs Technical Workshop Webinar

This session will walk through the full SoC development lifecycle using nanoSoC, an Arm-based reference design, and showcase how silicon-proven Cadence workflows and GlobalFoundries technology available through CMC can reduce design barriers and accelerate innovation.

Key Takeaways

• Understanding the full SoC development lifecycle — from concept to fabrication
• How nanoSoC enables IP reuse for faster prototyping
• Leveraging silicon-proven Cadence workflows through CMC
• Integrating AI/ML accelerators and sensor analog front-ends
• Simplifying tape-out for research and early-stage hardware platforms

Attendees will learn how reusable IP and maintained tool environments support faster prototyping, with real examples of AI/ML accelerator integration and sensor analog front-end interfacing.

Ideal for SoC architects, chip designers, researchers, and hardware developers exploring experimental or early-stage SoC projects.

Presenter & Host

John Darlington
Lead, SoC Labs — University of Southampton

John Darlington is part of the Electronics and Computer Science department at the University of Southampton and has collaborated with Arm for over 18 years. He leads the global SoC Labs community, connecting more than 120 universities working with reusable Arm-based hardware design, and develops reference SoC architectures in close collaboration with industry.

Daniel Newbrook
Senior ASIC Design Engineer — University of Southampton

Daniel Newbrook specializes in low-power ASIC design and reusable SoC architectures for hardware accelerator integration. He supports research teams developing modular, cost-efficient silicon prototyping solutions.

Register here!